Synopsys CoreTools vW-2024.09-SP2 | 663.7 mb
新思科技公司作为面向SoC设计提供高质量、硅验证半导体IP解决方案的领先供应商，正式发布coreTools vW-2024.09-SP2——这是一套用于基于知识型设计与验证流程的知识产权（IP）封装集成工具集。
coreTools系列包含：
coreBuilder——强大的IP封装工具，允许设计人员捕获IP的知识架构和设计意图，并提供图形化或命令式IP配置菜单。该工具支持封装IP所需的所有不同模型视图，可降低IP支持成本，提升质量，其封装的IP完全符合IP-XACT规范。
coreAssembler——开放式IP组装工具，可自动生成互连配置的RTL源代码，记录模块/系统配置细节并创建设计测试平台。与coreBuilder结合使用时可封装完整子系统形成coreKits组件库，助力快速构建市场应用可配置平台。除组装配置外，设计人员还可生成定制化初始测试平台以即刻开展设计验证，同时能输出符合IP-XACT标准的XML文件。
coreConsultant——专用于配置、实施和验证coreBuilder封装IP模块的实用工具包，亦可生成对应IP模块的IP-XACT XML文件。
新思科技coreTools系列作为完整的IP封装集成工具集，可无缝嵌入基于知识型的设计与验证流程中。通过该工具组，设计人员在使用IP时能获得最大效能提升。基于IP封装组件的设计与验证流程可近乎完全消除配置错误和子系统集成风险，实践数据显示该方案可使SoC/平台设计周期缩短60%以上，并在设计实现阶段达到最优质量结果（QoR）。
新思科技公司是全球半导体设计自动化（EDA）软件的领导者，为电子市场提供技术领先的芯片设计与验证平台，助力复杂片上系统（SoC）开发。其IP核与设计服务可显著简化设计流程并加速产品上市周期。公司总部位于加利福尼亚州山景城，在北美、欧洲、日本及亚洲设有60余个分支机构。
发行商： Synopsys Inc.
产品名称： coreTools
版本： vW-2024.09-SP2
支持架构： x86_64
Synopsys CoreTools vW-2024.09-SP2 | 663.7 mb
Synopsys Inc., a leading provider of high-quality, silicon-proven semiconductor IP solutions for SoC designs, has released coreTools vW-2024.09-SP2 is a set of intellectual property (IP) packaging and integration tools for use in a knowledge-based design and verification flow.
The coreTool family includes:
coreBuilder – a robust packaging tool that allows designers to capture the knowledge and design intent of the IP and provide graphical or command based configuration menus for the IP. It supports the packaging of all the different model views of the IP needed engineering teams. This reduces IP support costs, improves quality and IP packaged with coreBuilder is fully compliant with the IP-XACT specification.
coreAssembler – an open IP assembly tool that automatically generates the interconnect and configured RTL, as well as documenting the block and system configuration details and design testbench. When combined with coreBuilder, entire subsystems can be packaged as coreKits enabling the easy creation configurable market targeted platforms. In addition to assembly and configuration designers are able to generate a starting testbench configured for the design so they can begin to validate there design. coreAssembler also will generate the IP-XACT XML for the design.
coreConsultant – the utility package for configuring, implementing and validating individual IP blocks packaged with coreBuilder. coreConsultant will also generate the IP-XACT XML for the IP block.
The Synopsys family of coreTools is a comprehensive set of intellectual property (IP) packaging and integration tools for
use in a knowledge-based design and verification flow. The tools enable designers to realize maximum productivity gains
when using IP in their desing. By using an IP-based design and verification flow with IP packaged for assembly, the risk
configuration, and subsystem integration errors is virtually eliminated, and designers have seen over a 60% reduction in
SoC or platform design time and achieve the highest QoR in the implementation of the design
Synopsys, Inc. is the world leader in electronic design automation (EDA) software for semiconductor design. The company delivers technology-leading semiconductor design and verification platforms to the global electronics market, enabling the development of complex systems-on-chips (SoCs). Synopsys also provides intellectual property and design services to simplify the design process and accelerate time-to-market for its customers. Synopsys is headquartered in Mountain View, California and has offices in more than 60 locations throughout North America, Europe, Japan and Asia.
Owner: Synopsys Inc.
Product Name: coreTools
Version: vW-2024.09-SP2
Supported Architectures: x86_64
Languages Supported: english
System Requirements: Linux *
Size: 663.7 mb
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